1. Field of the Invention
The present invention relates to a method of thinning semiconductor wafers. More specifically, the present invention relates to a method of supporting bumped semiconductor wafers during a wafer thinning process using a mold compound which also acts as an underfill material in flip-chip mounting.
2. State of the Art
In order to increase production rates and to reduce costs for the manufacturing of integrated circuit semiconductor dice, a multitude of semiconductor dice are typically fabricated at one time onto a wafer comprising a semiconducting substrate (e.g., silicon or gallium arsenide) through methods well known in the art. Referring to drawing FIGS. 1 and 1A, the wafer 10 includes an active surface 15 where the semiconductor dice 20 reside and a back side 17. After fabrication, individual semiconductor die 20, commonly referred to as dice in the plurality or a die 20 in the singular, are typically separated from the wafer by sawing the wafer along boundary or scribe lines (streets) formed between each semiconductor die 20. Once separated, the semiconductor dice 20 can be packaged in various configurations, including smart-card packages and packages containing more than one semiconductor die 20, also known as multi-chip modules (MCMs).
The demand for smaller, higher performance semiconductor dice which support portable communications devices, including memory cards, smart cards, cellular telephones, and portable computing and gaming devices, has motivated the development of new techniques for producing smaller and thinner semiconductor dice from thinned wafers.
In addition to thinner profile advantages, there are other important benefits to reducing the thickness of a silicon semiconductor die in terms of enhancements to device performance and reliability. One of the major problems in increasing the speed and power of a chip is the removal of heat, particularly since semiconductor materials are generally poor thermal conductors. Nearly all semiconductor material is theoretically susceptible to thinning, as the performance characteristics of the semiconductor die are basically contained in 2-3 μm of active circuitry. Thinning a semiconductor die reduces the serial thermal resistance between the active circuitry on the front side or active surface of the semiconductor die and the back side of the semiconductor die, making for faster thermal transfer. Thinner semiconductor die may also aid problems caused by mismatches between coefficients of thermal expansion (CTE) of materials within a packaged semiconductor die. In this regard, thinner semiconductor dice are less prone to bond and silicon fracture because a reduced semiconductor die thickness allows the semiconductor die to flex with the substrate or board to which it is mounted. Thus, the semiconductor die thinning process can dramatically decrease the chances of thermal cycling-induced bond stress as well as reduce the chances of semiconductor die cracking.
A competing trend in current wafer manufacturing is to increase wafer size in order to reduce the costs of manufacturing an individual semiconductor die. At the present, wafers are typically around eight inches (8″) in diameter. Since silicon and gallium arsenide are relatively brittle materials, a minimum thickness of the wafer is required in order to handle a wafer of this size without breaking it. Since wafers having a diameter of approximately twelve inches (12″) are being used in the manufacture of semiconductor dice, thicker silicon wafers are required to withstand wafer handling and manufacturing processes.
With the lowest possible package profile thickness and size as the goal for the semiconductor die, however, the substrate thicknesses required for larger diameter wafers to be able to withstand wafer handling and manufacturing processes may not be suitable for some electronics applications. One way of reducing the thickness of such packages is to use semiconductor dice that are as thin as possible manufactured from wafers which are as thin as possible.
Typically, thin semiconductor dice are produced from thinned wafers, the wafer being thinned while in wafer form using a mechanical surface grinding (backgrinding) process, although chemical or plasma etching methods are sometimes used. Grinding is advantageous in that it can reduce wafer thickness accurately and at a relatively significant rate, making it a very affordable and simple process. Grinding also suffers from several disadvantages, however. Protective measures must be taken to ensure the circuit pattern-formed active surface 15 of the wafer is not stained or injured with grinding trashes, etc. Further, backgrinding can induce significant stress and damage the silicon wafer unless some form of support for the wafer is provided.
Referring to drawing FIG. 2A, illustrated is a backgrinding apparatus for thinning a semiconductor wafer 10. The basic elements of a backgrinding apparatus comprise a holding chuck 51, which may apply a vacuum force to hold the wafer, and a grinding wheel 52. In a representative wafer backgrinding process, a semiconductor wafer is placed between the holding chuck 51 and the grinding wheel 52 wherein the exposed surface on the back side 17 of a semiconductor wafer 10 is thinned to a desired thickness by the mechanical action of a grinding wheel. This process may also be extended to involve chemical mechanical polishing (CMP).
Illustrated in drawing FIG. 2B is a side view of semiconductor wafer 10 shown schematically wherein a thickness 17a of the inactive back side surface 17 of a semiconductor wafer 10 has been ground away.
In processing the semiconductor wafer, a protective member or submount can be previously adhered to the active surface 15 of the semiconductor wafer to protect the circuitry of the semiconductor dice formed on the semiconductor wafer. Protective members known in the art include adhesive tapes (such as UV tape) and a variety of resists, while submounts are typically formed of wax, glass, quartz, sapphire, metal, alumina, gallium arsenide or silicon and are secured to the wafer by an adhesive or bonding material. After backgrinding, a cleaning fluid is generally used to remove wafer debris and cool the semiconductor wafer. The cleaning fluid is subsequently dried, typically through a light source such as a halogen lamp. The protective tape, resist or submount is then removed from the active surface of the semiconductor die formed on the semiconductor wafer.
Although these prior art protective members provide a certain degree of support and possibly some cushioning during the backgrinding of the semiconductor wafer, their use is less than optimal for some applications. Areas of improvement include convenience and cost of use, increased structural support during grinding, ease of removal after the grinding process, and compatibility with other chip and/or fabrication steps. Tapes in particular pose challenges because of their high adhesive strength and the compressive stress they tend to induce on thinned semiconductor wafers.
A variety of methods exist for thinning a semiconductor wafer and for thinning an individual semiconductor die. U.S. Pat. No. 6,030,485 to Yamada relates to a method and apparatus for a wafer grinding process that uses an ultraviolet—(UV) sensitive tape to support the semiconductor wafer and protect circuitry elements during the grinding process. The UV-sensitive tape is manufactured with an adhesive agent that is reactive with ultraviolet rays and heat used in the drying process so as that the adhesive agent becomes less adhesive, thus allowing the tape to be peeled off.
U.S. Pat. No. 5,324,687 to Wojnarowski discloses a method of thinning semiconductor dice wherein the semiconductor dice are first adhesively mounted in die carriers made of removable or dissolvable material such as glass, metal, ceramics, etc. The front sides of the semiconductor dice are then adhered to a dielectric layer which, in turn, is overlaid with a resin layer followed by a holding layer made of a strong stiff material, such as magnetic metal. The semiconductor dice are then thinned by removing portions of the back surface of the semiconductor die and the carrier layer simultaneously. After a base or heat sink is bonded to the back of the semiconductor die, the holding member is detached by various methods, including chemically or electrochemically etching the holding member away, or by induction heating.
U.S. Pat. No. 5,389,579 to Wells discloses a method for single-sided polishing of a semiconductor wafer using double-sided polishing equipment in order to achieve flatter polished wafers. In Wells, a protective oxide coating is grown on one side of the wafer while the semiconductor material on the other side is left exposed. The wafer is then subjected to a two-sided grinding step wherein a polishing slurry removes semiconductor material from the exposed side while the oxide layer prevents the polishing of the second side of the semiconductor wafer.
U.S. Pat. No. 5,250,843 to Eichelberger outlines a semiconductor die thinning process where the semiconductor dice are placed face down and attached to a glass plate by an adhesive. The semiconductor dice and plate are then coated with a sealing layer to protect against material being lodged under the semiconductor die and to buffer the edges of the semiconductor dice. The semiconductor dice each further have a side protection material applied to prevent any possible lapping material from contacting the active surface of the semiconductor die during the lapping (backgrinding) process.
U.S. Pat. No. 5,127,984 to Asetta et al. discloses a thinning process wherein a high melting temperature wax is used as a bonding agent to bond a wafer to a quartz, glass, sapphire or metal submount. The wax, in non-water soluable semi-liquid format, is applied to a surface of a spinning semiconductor wafer, the semiconductor wafer spinning so as to ensure a uniform layer of the wax. The submount is placed on the wax layer and then the assembly is heated in a vacuum environment to remove air voids in the layer. Any excess wax is removed with solvent. To detach the wax and submount after grinding, the submount is heated until the wax softens and is liquified, thereby weakening the wax bond. The semiconductor wafer is then pushed from the submount onto a nonstick platform surface.
U.S. Pat. No. 5,273,940 to Sanders discloses a method for reducing the thickness of a plurality of semiconductor dice during the formation of a semiconductor die package. The method of Sanders entails electrically and physically coupling a plurality of unthinned semiconductor dice to the surface of a semiconductor substrate through conductive bumps, leaving the back side of the semiconductor dice exposed. The semiconductor dice and substrate are then encapsulated, the encapsulation material serving to protect the semiconductor dice, including the active side circuitry of individual semiconductor die, as well as protecting the semiconductor die interconnections to the mounting substrate and further fastening the semiconductor dice. Thereafter, a grinding disk removes material from the back side of each semiconductor die to produce a low profile multi-chip package.
Grinding before semiconductor dice singulation has its limits, however, since the scraping away of silicon material can distort the silicon crystal lattice of the semiconductor wafer, resulting in stress fields that can ultimately degrade semiconductor die performance. Wet-etching is typically used to reduce some of the post-grinding residual damage. In this process, about 50 μm of material can be further removed from the semiconductor wafer to eliminate the stress concentration and crack initiation points in the crystal lattice, provided the wafer remains relatively thick so as to withstand the demands of handling. Exemplary wet-etching processes used in combination with the mechanical removal of silicon through backgrinding are disclosed in U.S. Pat. No. 5,480,842 to Clifton et al., and in U.S. Pat. No. 5,268,065 to Grupen-Shemansky.
More recently, an etching process using atmospheric downstream plasma (ADP) dry chemical etching (DCE) technology has been developed. ADP-DCE has thinning capabilities of 2 mils and below while additionally offering the stress-reducing benefits of wet chemical etching. While demonstrating significant advantages, throughput under ADP-DCE is lower than that of grinding as ADP-DCE does not provide similar silicon removal rates. Furthermore, the ADP-DCE process uses environmentally-unfriendly fluorine-based chemicals.
Another recent innovation in the art of thinning wafers uses a “dicing before grinding” (DBG) method to grind semiconductor wafers to very thin levels (approaching 30 μm). The DBG method advantageously avoids etching and the handling of fragile thinned semiconductor wafers after grinding. In this process, a wafer is scored (diced) to a depth of approximately 50 μm to separate the semiconductor die. The diced active surface is then protectively taped in order to shield it during grinding, then a second layer of tape is applied to hold the diced semiconductor dice. The semiconductor wafer is then subjected to a back grinding process until the scores are reached, at which point the semiconductor dice automatically separate. The semiconductor dice that result are reportedly stronger than semiconductor dice that have been subjected to chemical etching.
The applicability of these exemplary methods, however, is challenging in the context of commonly used flip-chip semiconductor die manufacturing processes, which may involve bumped semiconductor wafers. Flip-chips, because of their capacity for low-profile and high-density interconnections, are being used in ever-increasing numbers.
Flip-chips are generally characterized as semiconductor dice with solder or other conductive bumps placed on I/O pads of the active surface of the semiconductor die and wherein mounting the semiconductor die involves flipping the semiconductor die over, aligning the semiconductor die with contact pads on a substrate, and applying heat to reflow (melt) the solder balls to establish bonding between the semiconductor die and the substrate.
Controlled-Collapse Chip Connection (C4) technology is one exemplary flip-chip technology which utilizes solder bumps deposited on solder wettable metal bond pads on the active surface of the semiconductor die in combination with a matching footprint of solder wettable contact pads or terminals on the substrate. The technology involves first, laying down a passivation layer on the surface of a semiconductor die which covers the bond pads where connections will be made between the semiconductor die and a substrate. Next, holes are formed in the passivation layer over the bond pads of the semiconductor die and metallization is deposited. Finally, solder bumps are deposited on the metallized areas of the semiconductor die and a preliminary reflow performed so that the bumps take on a semi-spherical shape. Later, after alignment with a substrate, a final reflow will form the semiconductor die-to-substrate connections.
An advantage in using flip-chip technology is that semiconductor die size can be kept to a minimum since the semiconductor die does not employ a traditional package body. Furthermore, electrical connections between a semiconductor die and a substrate are confined to an area of the substrate which does not exceed the size of the semiconductor die. There is no need for wire bonds or for any kind of external lead in order to couple the semiconductor die to the substrate. Flip-chip technology is further considered advantageous in certain applications because the I/O pads are distributed over the entire semiconductor die surface rather than being confined to the periphery of the semiconductor die as in wire bonding and most tape-automated bonding (TAB) techniques. Finally, conventional solder-bumped flip-chip arrangements allow a high density of connections per given area of active surface of the semiconductor die, and the least amount of semiconductor die-to-carrier connection time because of the ability to effect all connections simultaneously.
When mounting a flip-chip semiconductor die to a substrate, the substrate is prepared with solder flux prior to “flipping” the semiconductor die over and aligning the solder bumps with the substrate terminals. All of the solder joints are then formed simultaneously by reflowing (melting) the solder to achieve electrical connection. Residual flux is then removed using an appropriate solvent.
To enhance the bond integrity formed by the bumps located between the flip-chip semiconductor die and the substrate, an underfill material typically comprised of a suitable polymer is introduced in the gap between the semiconductor die and the substrate. One area of concern in flip-chip packaging is thermal expansions resulting from CTE mismatches between the underfill, the semiconductor die and the substrate. If these materials are not suitably thermally matched, there may be undue strains at the bumped electrical connections which could lead to failure of the packaged semiconductor device.
The increased use of flip-chip semiconductor dice pose additional obstacles for certain wafer manufacturing processes in that it is presently extremely difficult to grind a wafer after it has been bumped. After bumping, the fragile nature of the bumped active surface of the wafer preclude conventional methods of taping, adhesive mounting, etc. Wafers can be thinned before bumping, but handling requirements for the bumping process serve to limit wafer thinness under traditional grinding methods to an estimated range of 250 through 500 μm thickness.
Additionally, flip-chip semiconductor dice may be chipped during dicing operations. The separated flip-chip semiconductor die may have, for example, rough edges as a result of the dicing process. A basic consideration when dicing or sawing a wafer is how much chipping of the semiconductor die can be tolerated. Chipping is observed on both the top side and back side of the semiconductor wafer. For a given saw process, chipping can vary drastically between these two sides. Top side chipping is readily visible on the active surface of a semiconductor wafer. It consists of scalloped-shaped chip outs along the edge of the saw kerf. Uncontrolled top side chipping of the semiconductor wafer directly correlates to assembly line yield losses. If the top side chipping of the semiconductor wafer is excessive, damage can result in damage to the active circuitry of the semiconductor dice on the semiconductor wafer, causing device failure or performance degradation. With the advent of thin surface mount components (TQFP, TSSOP), there is an apparent trend to significantly reduce semiconductor wafer thickness. However, chipping of the semiconductor wafer is more prevalent in thinner wafers as a result of silicon stress.
After a flip-chip semiconductor die is separated from the other flip-chip semiconductor dice of the semiconductor wafer, the flip-chip semiconductor die is then packaged and/or mounted to a substrate, such as a printed circuit board. As a result of chipping, the flip-chip semiconductor die may suffer various forms of damage at any point subsequent to the dicing process. For example, the flip-chip semiconductor die may be damaged while it is being handled prior to mounting or packaging.
Several recent semiconductor wafer thinning methods have been developed to overcome the problems associated with thinning bumped semiconductor wafers. Certain of these methods use varying etching processes in combination with a non-contact holding method for supporting the bumped area of the semiconductor wafer during the etching process. In each case, the semiconductor wafer is positioned face down on a stream of inert gas which levitates the semiconductor wafer, the gas stream acting to protect both the front and side edges of the semiconductor wafer during etching. While satisfactorily protecting the bumped surface of the semiconductor wafer during thinning, these methods utilize comparatively complex apparatus and are, therefore, relatively expensive to operate. In addition, the rate of removal of silicon material using these methods is inferior to that of a conventional grinding process.
Accordingly, what is needed within the art is a method of thinning a bumped semiconductor wafer that allows for rapid, inexpensive and accurate removal of semiconductor wafer material while protecting the bumped surface and the sides of the semiconductor wafer. Further needed is a method which minimizes the risk of semiconductor wafer breakage during handling. Ideally, such a method would be compatible with conventional semiconductor wafer thinning procedures and equipment, result in as few process steps as feasible, be suitable for use in high throughput production, and result in very thin semiconductor die suitable for stacking or use in very low-profile semiconductor die packages.